A broad range of products incorporate analog to digital and digital to analog converters. Performance expectations of these products are constantly driving designs to achieve greater linearity and bandwidth while limiting or reducing power consumption. Oversampling delta sigma (ΔΣ) modulators with feedback support analog-to-digital (A/D) and digital to analog (D/A) architectures to meet these needs. Oversampling converters offer lower power consumption and complexity than pipelined A/D converters. However, technology imposes limits on the oversampling ratio (OSR). A consequence is that when the OSR is low, and resolution and bandwidth need to be high, multibit quantization is needed with oversampling modulators. However, mismatch-induced errors in multibit digital to analog converters (DAC)s for multibit quantization can be the driver limiting the spurious-free dynamic range (SFDR). In order to match the SFDR of the modulator's linearity, linearization techniques are used. Dynamic element matching is one of these. Dynamic element matching (DEM) is a process of dynamically selecting the unit elements of a multilevel DAC to produce an output level corresponding to a digital code. Although dynamic element matching increases chip area and complexity, the increases are relatively small. Dynamic element matching employs the averaging intrinsic to oversampling modulators to decorrelate mismatch-induced DAC errors from the input signal and move noise power out of the signal band. Several algorithms exist to dynamically select the unit elements. One of the DEM techniques is data weighted average (DWA). It is not only used to shuffle, but also applied to filter the DAC mismatch error out of the signal band by using a scrambler to change the connections of the thermometer coded quantizer outputs before they are applied on the feedback DAC. However, for delta sigma modulators at slow input signal, the DWA algorithm generates strong in-band signal-dependent tones that degrade the signal-to-noise-plus-distortion ratio (SNDR).
A variation of the DWA algorithm is the partitioned DWA (P-DWA). The P-DWA algorithm is based on DWA; it decreases the delay of DEM circuitry, but at the cost of an increase in inband tones. For the P-DWA algorithm, the multibit DAC is divided into two partitions, each containing half of the unit elements. DWA is performed independently within each partition to determine which set of unit elements in each partition is selected to generate a DAC output. To obtain the digital input codes for each of the partitions, the overall digital input (which encodes the desired output level as a thermometer code) is split into two equal parts. The even bits of the digital input are used as the inputs to the first partition, and the odd bits are allocated to the second partition. A concern in the case of P-DWA is the effect of systematic mismatch among the average capacitor values in the two partitions. If this mismatch becomes linearly increased compared to the mismatch between the unit elements within each partition, in-band tones are added to the overall in-band quantization noise power. While the P-DWA algorithm can reduce the time delay by half, it increases in-band tones and generates a DC signal.
FIG. 1 is a fully differential switched-capacitor implementation of the fifth-order cascaded delta sigma (ΣΔ) modulator integrated in CMOS technology. As noted previously, because of the noise shaping provided by each stage in this architecture, the circuits in the first stage are subject to the most stringent requirements. This section therefore stage, with special consideration given to the difficulties encountered in the design for operation from a low supply voltage.
FIG. 2 is a DWA circuit from Zhang, Z., and Temes, G. C., ‘A Segmented Data-Weighted-Averaging Technique’, ISCAS, May 2007, New Orleans, pp. 481-484. While displaying limitations, it provides good tonal behavior in a P-DWA circuit device (102 in FIG. 1) comprising at least two inputs of multiplexer (MUX) provided signals from analog-to-digital converter (as quantizer) 101 in FIG. 1; at least two MUXs; at least two inputs per shifter, selecting between the signals of at least a first input of MUXs and the signals of at least a second input of MUXs providing inputs to a DAC 103 (and 104, 105) in FIG. 1; at least two pointer generator, generating a rotation pointer indicating where each input should be rotated during the next cycle, whereby outputs of the plurality of shifters direct to a plurality of outputs, whereby non-overlap alternation of the signals of the at least a first shifter block and the at least a second shifter block with double sampling quantization and DEM removes DC components but increases instability by introducing the additional loop delay of MUXs.
FIG. 3 is a 4-bit DWA circuit containing a pointer generator and a shifter. The pointer generator generates the rotation pointer indicating where each input bit, q(3)-q(0), should be rotated during the next clock cycle. The shifter rotates each input bit to the proper position through the binary-weighted control code sh(1)-sh(0). In some DWA implementations, instead of a shifter, a coder is used to directly map the quantizer output bits through the MUX to the DAC inputs d(3)-d(0), but this implementation is slower than the shifter-based one. Also, such coder-based DWA system introduces more loop delay in a continuous-time DSM, making it less stable. In an SC realization, settling errors are introduced in the integrating phase. Hence, shifter-based DWA implementation is often preferred.
Each of these approaches has consequences such as loop delay; stability impacts, DC signals and notable power consumption. What is needed are techniques for a double-sampling AE modulator architecture giving improved performance without increasing power consumption.